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EngineeringVLSI / Semiconductor / Digital Circuit DesignOn-site
Digital Circuit Design Engineer Fresher Jobs – Lakshya Software Technologies Pvt. Ltd.
Great news for freshers! Lakshya Software Technologies Pvt. Ltd. is hiring for Digital Circuit Design Engineer Fresher Jobs in Hyderabad, Telangana, India. Read the full requirements below and apply before ASAP.
| Company | Lakshya Software Technologies Pvt. Ltd. |
| Job Category | Engineering |
| Domain | VLSI / Semiconductor / Digital Circuit Design |
| Qualification | B.Tech / M.Tech |
| Experience | 1–3 Years |
| Salary | Best in Industry |
| Job Type | Full-time |
| Work Mode | On-site |
| Primary Location | Hyderabad, Telangana, India |
| Target Locations | Hyderabad, Telangana |
| Last Date | ASAP |
| Application Mode | LinkedIn Easy Apply |
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About the Role
Responsible for digital circuit design verification, gate-level simulation, circuit characterization, timing analysis, and debugging. The role involves working with circuit schematics, SPICE simulators, Verilog models, and transistor-level or gate-level fixes.
Basic Qualifications
- B.Tech / M.Tech in a relevant engineering discipline.
- 1–3 years of relevant experience.
- Hands-on experience with digital circuit design and simulation.
- Understanding of circuit schematics and circuit behaviour.
Preferred Qualifications
- Familiarity with Universal Verification Methodology (UVM).
- Experience with SystemVerilog Assertions.
- Knowledge of static timing analysis and timing libraries.
- Experience with latch-based designs.
Responsibilities
- Develop and understand building block and memory schematics.
- Run circuit simulations using SPICE simulators.
- Perform DC and transient analysis.
- Analyse circuit behaviour from schematics.
- Perform circuit characterization and timing analysis.
- Conduct gate-level simulations with SDF back annotation.
- Debug SDF annotation issues and improve annotation coverage.
- Debug gate-level simulation failures and identify root causes.
- Analyse latch-based designs and their timing requirements.
- Perform what-if analysis and implement suitable fixes.
- Debug failures and provide fixes at gate or transistor level.
- Correlate SPICE simulation results with gate-level simulation results.
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Required Skills
- Digital Circuit Design.
- Circuit Schematics.
- SPICE Simulation.
- DC and Transient Analysis.
- Verilog MOS Switch-Level Models.
- Gate-Level Simulation.
- SDF Back Annotation.
- Static Timing Analysis.
- Circuit Debugging.
- Timing Analysis.
- SystemVerilog Assertions.
Preferred Skills
- Universal Verification Methodology (UVM).
- Memory Circuit Design.
- Circuit Characterization.
- Timing Libraries and Timing Arcs.
- Latch-Based Design.
- Netlist Simulation.
- Zero-delay, Unit-delay and Path-delay Simulation.- Strong Verbal and Written Communication.
Benefits
- Not Specified.
Selection Process
- In-person interview.
- Technical evaluation of relevant VLSI and digital circuit design skills.
- Further selection rounds as per company requirements.
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Posted via SLGhiring · Last date to apply: ASAP
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