ti Steps – RTL Design Engineer
ti Steps
About the Role
ti Steps is hiring RTL Design Engineers to develop and implement RTL code for digital IPs and SoCs. The role involves Verilog/SystemVerilog coding, IP integration, RTL optimization, verification support, and collaboration with design teams to build high-quality semiconductor solutions.
Basic Qualifications
B.E./B.Tech or M.Tech in ECE, Electrical Engineering, VLSI, or related field.
0–3 years of relevant experience.
Strong understanding of Digital Logic Design and Computer Architecture.
Experience with Verilog/SystemVerilog.
Basic knowledge of synthesis tools and scripting.
Preferred Qualifications
Familiarity with Lint and CDC checks.
Knowledge of Perl, Tcl, or Python scripting.
Good debugging and analytical skills.
Strong communication and teamwork abilities.
Interest in RTL Design and semiconductor technologies.
Responsibilities
Develop RTL code using Verilog/SystemVerilog.
Implement and integrate digital IPs based on specifications.
Ensure synthesizable, high-quality RTL designs.
Support verification and debugging during simulation and emulation.
Participate in design reviews and documentation.
Collaborate with verification and hardware teams.
Required Skills
RTL Design
Verilog
SystemVerilog
Digital Logic Design
Computer Architecture
Scripting
Python
Perl
Tcl
Synthesis
Lint
CDC
Preferred Skills
SoC Design
IP Integration
Debugging
Simulation
Emulation
Problem Solving
Team Collaboration
Documentation
Benefits
Competitive salary package.
Opportunity to work on VLSI and SoC design projects.
Exposure to industry-standard RTL design methodologies.
Career growth in semiconductor engineering.
Collaborative engineering environment.
Selection Process
Online Application
Resume Screening
Technical Assessment
Technical Interview
HR Interview
Final Selection
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